Difference between revisions of "Hardware/Memory Interface"

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(New page: {{Infobox MMIO | ppc = Full | base = 0x0c004000 | len = 0x80 | bits = 16/32 | ppcirq = 7 }} {{hwstub}} {{yagcd}})
 
(Added some basic info from YAGCD)
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Protected memory is always 1 page long (page size is 1024 bytes), and you can specify only 4 protected regions. If the CPU tries to access the protected region in a way that is not allowed, an external interrupt will be raised. Because there are only 4 protected regions, there are a total of 4 possible interrupts which are called MEM_0, MEM_1, MEM_2 and MEM_3.
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== Registers ==
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{{reg32 | MI_PROT_RGN0 | addr = 0x0C004000 | hifields = 1 | lofields = 1 |
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|16  |
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|R/W |
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|Low 16 bits of protected address ||
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|16  |
 +
|R/W |
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|High 16 bits of protected address |
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|}}
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{{reg32 | MI_PROT_RGN1 | addr = 0x0C004004 | hifields = 1 | lofields = 1 |
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|16  |
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|R/W |
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|Low 16 bits of protected address ||
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|16  |
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|R/W |
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|High 16 bits of protected address |
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|}}
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{{reg32 | MI_PROT_RGN2 | addr = 0x0C004008 | hifields = 1 | lofields = 1 |
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|16  |
 +
|R/W |
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|Low 16 bits of protected address ||
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|16  |
 +
|R/W |
 +
|High 16 bits of protected address |
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|}}
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{{reg32 | MI_PROT_RGN3 | addr = 0x0C00400C | hifields = 1 | lofields = 1 |
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|16  |
 +
|R/W |
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|Low 16 bits of protected address ||
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|16  |
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|R/W |
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|High 16 bits of protected address |
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|}}
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{{reg16 | MI_PROT_TYPE | addr = 0x0C004010 | fields = 5 |
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|8 |2  |2  |2  |2  |
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|U |R/W |R/W |R/W |R/W |
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|  |Ch3 |Ch2 |Ch1 |Ch0 |
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|}}
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{{regdesc
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|ChX|00: Access Denied, 01: Read Only, 10: Write Only, 11: Read/Write
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}}

Revision as of 05:27, 6 July 2010

Memory Interface
Access
BroadwayFull
StarletNone
Registers
Base0x0c004000
Length0x80
Access size16/32 bits
Byte orderBig Endian
IRQs
Broadway7
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Protected memory is always 1 page long (page size is 1024 bytes), and you can specify only 4 protected regions. If the CPU tries to access the protected region in a way that is not allowed, an external interrupt will be raised. Because there are only 4 protected regions, there are a total of 4 possible interrupts which are called MEM_0, MEM_1, MEM_2 and MEM_3.

Registers

MI_PROT_RGN0 (0x0C004000)
  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Access R/W
Field Low 16 bits of protected address
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access R/W
Field High 16 bits of protected address

MI_PROT_RGN1 (0x0C004004)
  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Access R/W
Field Low 16 bits of protected address
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access R/W
Field High 16 bits of protected address

MI_PROT_RGN2 (0x0C004008)
  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Access R/W
Field Low 16 bits of protected address
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access R/W
Field High 16 bits of protected address

MI_PROT_RGN3 (0x0C00400C)
  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Access R/W
Field Low 16 bits of protected address
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access R/W
Field High 16 bits of protected address


MI_PROT_TYPE (0x0C004010)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access U R/W R/W R/W R/W
Field Ch3 Ch2 Ch1 Ch0
Field Description
ChX 00: Access Denied, 01: Read Only, 10: Write Only, 11: Read/Write