Difference between revisions of "Hardware/Memory Controller"

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(Started description of Memory Controller interface)
 
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These registers contain various settings relevant to configuring system memory (and perhaps some aspects of the AHB).
 
These registers contain various settings relevant to configuring system memory (and perhaps some aspects of the AHB).
 
[[boot1]] seems responsible for initially configuring a lot of these registers during the boot process - most likely for setting the DDR memory timings.
 
[[boot1]] seems responsible for initially configuring a lot of these registers during the boot process - most likely for setting the DDR memory timings.
The IOS[58] kernel exposes syscall 0x57 for writing to this register space, which only appears to be used by the STM module.
+
In general, IOS (including BC/MIOS) seem to interact with these early when booting.
 +
The IOS[58] kernel also exposes syscall 0x57 for writing to this register space, which only appears to be used by the STM module.
  
 
Some of these register banks (SEQ/BIST/PERF) are not directly mapped into memory, but are instead accessed using a corresponding pair of registers.
 
Some of these register banks (SEQ/BIST/PERF) are not directly mapped into memory, but are instead accessed using a corresponding pair of registers.

Revision as of 09:48, 8 November 2019

Memory Controller
Access
Broadway???
StarletFull
Registers
Base0x0d8b4200
Length0xcc (?)
Access size16 bits
Byte orderBig Endian
This box: view  talk  edit
SEQ
Access
Broadway???
StarletFull
Registers
BaseN/A
Length???
Access size16 bits
Byte orderBig Endian
This box: view  talk  edit
BIST
Access
Broadway???
StarletFull
Registers
BaseN/A
Length???
Access size16 bits
Byte orderBig Endian
This box: view  talk  edit
PERF
Access
Broadway???
StarletFull
Registers
BaseN/A
Length???
Access size16 bits
Byte orderBig Endian
This box: view  talk  edit
ARB_EX (?)
Access
Broadway???
Starlet???
Registers
Base???
Length???
Access size??? bits
Byte orderBig Endian
This box: view  talk  edit


These registers contain various settings relevant to configuring system memory (and perhaps some aspects of the AHB). boot1 seems responsible for initially configuring a lot of these registers during the boot process - most likely for setting the DDR memory timings. In general, IOS (including BC/MIOS) seem to interact with these early when booting. The IOS[58] kernel also exposes syscall 0x57 for writing to this register space, which only appears to be used by the STM module.

Some of these register banks (SEQ/BIST/PERF) are not directly mapped into memory, but are instead accessed using a corresponding pair of registers. Although the memory controller registers are actually mapped and available to ARM starting at 0x0d8b4200, some [all?] of these indirect accesses are performed starting with another pair in the Memory Interface registers.


Memory Controller Base Registers
Address Bits Name Description
0x0d8b4200 16 MEM_COMPAT
0x0d8b4202 16 MEM_PROT_REG
0x0d8b4204 16 MEM_PROT_SPL SPL (?) protection enabled/disable
0x0d8b4206 16 MEM_PROT_SPL_BASE SPL (?) protection base address
0x0d8b4208 16 MEM_PROT_SPL_END SPL (?) protection end address
0x0d8b420a 16 MEM_PROT_DDR DDR protection enable/disable
0x0d8b420c 16 MEM_PROT_DDR_BASE DDR protection base address
0x0d8b420e 16 MEM_PROT_DDR_END DDR protection end address
0x0d8b4210 16 MEM_COLSEL
0x0d8b4212 16 MEM_ROWSEL
0x0d8b4214 16 MEM_BANKSEL
0x0d8b4216 16 MEM_RANKSEL
0x0d8b4218 16 MEM_COLMSK
0x0d8b421a 16 MEM_ROWMSK
0x0d8b421c 16 MEM_BANKMSK
0x0d8b421e 16 MEM_PROT_SPL_ERR
0x0d8b4220 16 MEM_PROT_DDR_ERR
0x0d8b4222 16 MEM_PROT_SPL_MSK
0x0d8b4224 16 MEM_PROT_DDR_MSK
0x0d8b4226 16 MEM_RFSH
0x0d8b4228 16 MEM_AHMFLUSH AHB flush request
0x0d8b422a 16 MEM_AHMFLUSH_ACK AHB flush request acknowledgment
0x0d8b4268 16 MEM_SEQRD_HWM
0x0d8b426a 16 MEM_SEQWR_HWM
0x0d8b426c 16 MEM_SEQCMD_HWM
0x0d8b426e 16 MEM_CPUAHM_WR_T
0x0d8b4270 16 MEM_DMAAHM_WR_T
0x0d8b4272 16 MEM_DMAAHM0_WR_T
0x0d8b4274 16 MEM_DMAAHM1_WR_T
0x0d8b4276 16 MEM_PI_WR_T
0x0d8b4278 16 MEM_PE_WR_T
0x0d8b427a 16 MEM_IO_WR_T
0x0d8b427c 16 MEM_DSP_WR_T
0x0d8b427e 16 MEM_ACC_WR_T
0x0d8b4280 16 MEM_ARB_MAXWR
0x0d8b4282 16 MEM_ARB_MINRD
0x0d8b4284 16 MEM_PROF_CPUAHM
0x0d8b4286 16 MEM_PROF_CPUAHM0
0x0d8b4288 16 MEM_PROF_DMAAHM
0x0d8b428a 16 MEM_PROF_DMAAHM0
0x0d8b428c 16 MEM_PROF_DMAAHM1
0x0d8b428e 16 MEM_PROF_PI
0x0d8b4290 16 MEM_PROF_VI
0x0d8b4292 16 MEM_PROF_IO
0x0d8b4294 16 MEM_PROF_DSP
0x0d8b4296 16 MEM_PROF_TC
0x0d8b4298 16 MEM_PROF_CP
0x0d8b429a 16 MEM_PROF_ACC
0x0d8b429c 16 MEM_RDPR_CPUAHM
0x0d8b429e 16 MEM_RDPR_CPUAHM0
0x0d8b42a0 16 MEM_RDPR_DMAAHM
0x0d8b42a2 16 MEM_RDPR_DMAAHM0
0x0d8b42a4 16 MEM_RDPR_DMAAHM1
0x0d8b42a6 16 MEM_RDPR_PI
0x0d8b42a8 16 MEM_RDPR_VI
0x0d8b42aa 16 MEM_RDPR_IO
0x0d8b42ac 16 MEM_RDPR_DSP
0x0d8b42ae 16 MEM_RDPR_TC
0x0d8b42b0 16 MEM_RDPR_CP
0x0d8b42b2 16 MEM_RDPR_ACC
0x0d8b42b4 16 MEM_ARB_MAXRD
0x0d8b42b6 16 MEM_ARB_MISC
0x0d8b42b8 16 MEM_ARAM_EMUL "ARAM Emulation" (?)
0x0d8b42ba 16 MEM_WRMUX
0x0d8b42bc 16 MEM_PERF
0x0d8b42be 16 MEM_PERF_READ
0x0d8b42c0 16 MEM_ARB_EXADDR
0x0d8b42c2 16 MEM_ARB_EXCMD
0x0d8b42c4 16 MEM_SEQ_DATA Data from read (or for pending write) on DDR SEQ
0x0d8b42c6 16 MEM_SEQ_ADDR Offset for access on DDR SEQ register space
0x0d8b42c8 16 MEM_BIST_DATA Data from read (or for pending write) on DDR BIST
0x0d8b42ca 16 MEM_BIST_ADDR Offset for access on DDR BIST register space

DDR SEQ Register Space

DDR BIST Register Space

DDR PERF Register Space