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Revision as of 09:11, 26 July 2010 by Randomdude
- IBM 'Broadway' 90 nm based on IBM's Power architecture.
- Runs at a speed of 729 MHz. Maximum Bandwidth is 1.9 GB/s.
- Bus to main memory: 243 MHz, 64 bits (maximum bandwidth: 1.9 GB/s)
- 32 KB 8-way set-associative L1 instruction cache
- 32 KB 8-way set-associative L1 data cache (can set up 16-kilobyte data scratch pad)
- Superscalar microprocessor with six execution units (floating-point unit, branching unit, system register unit, load/store unit, two integer units)
- DMA unit (15-entry DMA request queue) used by 16-kilobyte data scratch pad
- Write-gather buffer for writing graphics command lists to the graphics chip
- Onboard 256-kilobyte 2-way set-associative L2 integrated cache
- Two, 32-bit integer units (IU)
- One floating point unit (FPU) (supports single precision (32-bit) and double precision (64-bit))
- The FPU supports paired single floating point (FP/PS)
- The FPU supports paired single multiply add (ps_madd). Most FP/PS instructions can be issued in each cycle and completed in three cycles.
- Fixed-point to floating-point conversion can be performed at the same time as FPU register load and store, with no loss in performance.
- The branch unit supports static branch prediction and dynamic branch prediction.
- When an instruction is stalled on data, the next instruction can be issued and executed. All instructions maintain program logic and will complete in the correct program order.
- Supports three L2 cache fetch modes: 32-Byte, 64-Byte, and 128-Byte.
- Supports these bus pipeline depth levels: level 2, level 3, and level 4.
Reference Information: Broadway is upward compatible with Nintendo GameCube’s CPU (Gekko).