Hardware/GX/Blitting Processor
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The Blitting Processor is a component of the Wii's GX subsystem. It is responsible for copying the EFB to the XFB, doing the RGBA->YCbCr conversion and scaling/antialiasing in the process.
BP (blitting processor) registers
The BP registers are accessed by writing a 8-bit value of 0x61 to the FIFO, followed by 32 bit value. This value is a bit weird - the high 8 bits are the register, and the low 24 bits are the register value.
EFB source registers
One can specify which part of the EFB is copied to the XFB or texture, using the following BP registers:
| GX_BP_EFB_BOXCOORD (0x49) | ||||||||||||||||||||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | U | R/W | R/W | |||||||||||||||||||||
| Field | Y | X | ||||||||||||||||||||||
- 0x49: coordinates to top left of rectangle in EFB that will be copied (packed format, unknown)
| GX_BP_EFB_BOXSIZE (0x4a) | ||||||||||||||||||||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | U | R/W | R/W | |||||||||||||||||||||
| Field | height-1 | width-1 | ||||||||||||||||||||||
- 0x4a: width and height-1 of rectangle to copy in EFB (again, unknown packed format)
XFB destination registers
The destination of the copy in the XFB is specified by the physical address of the XFB and the row stride (basically width of row, but no scaling appled).
| GX_BP_XFB_ADDR (0x4B) | |
| 230 | |
| Access | R/W |
- 0x4b: Address of destination (XFB). BEWARE: Address is a PHYSICAL address, SHIFTED RIGHT by 5.
| GX_BP_XFB_STRIDE (0x4D) | ||
| 2310 | 90 | |
| Access | U | R/W |
- 0x4d: Low 10 bits specify row stride of destination.
Copy control register
| GX_BP_COPY_CONTROL (0x52) | ||||||||||||||||||||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | U | W | R/W | U | ||||||||||||||||||||
| Field | Start | Clr | ||||||||||||||||||||||
- 0x52: This register starts a copy. Important bits:
| Field | Description |
| Start | Writing both of these bits to 1 will start a copy. |
| Clr | Enables or disables clearing of the EFB during the copy. |
Copy filter registers
| GX_BP_FILTER_0 (0x01) | |
| 230 | |
| Access | R/W |
| GX_BP_FILTER_1 (0x02) | |
| 230 | |
| Access | R/W |
| GX_BP_FILTER_2 (0x03) | |
| 230 | |
| Access | R/W |
| GX_BP_FILTER_3 (0x04) | |
| 230 | |
| Access | R/W |
Registers 0x01-0x04 are used for tricks like antialiasing. For a plain copy (i.e. no antialiasing) set all for to 0x666666.
Vertical filter registers
| GX_BP_VFILTER_0 (0x53) | ||||||||||||||||||||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | R/W | R/W | R/W | R/W | ||||||||||||||||||||
| Field | f3 | f2 | f1 | f0 | ||||||||||||||||||||
| GX_BP_VFILTER_0 (0x54) | ||||||||||||||||||||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | U | R/W | R/W | R/W | ||||||||||||||||||||
| Field | f6 | f5 | f4 | |||||||||||||||||||||
Like the filter registers, these vertical filter registers must be set up properly for you to see anything at all. Default values for no fancy operations are as follows:
| Field | Description |
| f0 | 0x00 |
| f1 | 0x00 |
| f2 | 0x15 |
| f3 | 0x16 |
| f4 | 0x15 |
| f5 | 0x00 |
| f6 | 0x00 |
Beginning a copy
The following must take place to do a copy:
- Setup clear and z clear registers (optional)
- Set source and destination registers
- Write to display copy control register to begin a copy
- Set clear, z, and control registers again (what? doubt necessary, libogc GX is stupid)